Multi-rate LDPC code system and method

ABSTRACT

A method for creating cyclic permutation matrices P ( 810 ), with an arbitrary size Z×Z set by a parameter Z5 and which are used to create one or more LDPC related matrices in OFDMA systems, comprising: defining an integer value Z; creating an initial matrix ( 810 ); creating a matrix ( 810 ) by using cyclic shifts to each row; repeating stage 3, up to Z−2 times as required, thus creating up to Z−2 matrices: P(o) . . . P(Z−I); creating an additional stairs matrix P(st). A method for using cyclic per-mutation matrixes P ( 840 ), with a fixed size Z×Z set by a parameter Z, and which are used to create one or more LDPC related matrices ( 820 ) in OFDMA systems, comprising: defining an integer value Z; storing in memory means an initial matrix ( 810 ) and its cyclic shifts permutations ( 840 ), thus keeping memory means matrices: P(o) . . . P(Z−I); storing an additional stairs matrix P(st) ( 840 ); using these matrices ( 810 ) to create LDPC related matrices ( 840 ) or LDPC operations.

This application is filed under 35 USC 371 and is based on, and claimsthe benefit of, International Application having a serial number ofPCT/IL2005/000679, which was filed on Jun. 24, 2005 and claimingpriority to U.S. Provisional Application for Patent filed on Jun. 25,2004 with a title of MULTI-RATE LDPC CODE FOR OFDMA PHY and assignedSer. No. 60/582,583 and U.S. Provisional Application for Patent filed onAug. 17, 2004 with a title of MULTI-RATE LDPC CODE FOR OFDMA PHY andassigned Ser. No. 60/601,956, all of which are incorporated herein byreference.

TECHNICAL FIELD

This invention relates to LDPC codes, and more specifically to suchcodes using new LDPC approaches with unique characteristics.

BACKGROUND ART

The Low Density Parity Check Code (LDPC) are known in the art forvarious applications. LDPC is an advanced error correcting linear code,which is used in encoding and decoding in order to detect and correcterrors.

LDPC can achieve similar or better performance than those of turbocodes, with lower decoder complexity.

Soft input soft output decoder and iterative decoding of the receiveddata block approaches can be used in LDPC.

LDPC can be implemented without using an interleaver.

Code rate can be changed in a relatively simple approach while usingLDPC.

The matrices, which represent block size and/or code rate, are easy todesign, and can be optimized to specific requirements.

Encoding is implemented by combining parity check bits and a datavector, thus creating a unique codeword vector. Upon receiving thecodeword vector, it is possible to detect and correct a number oferrors.

LDPC can be implemented in OFDMA systems in the encoding and decodingmeans, for better performance with an easier implementation.

In particular, LDPC can be used in OFDMA systems according to the 802.16standard.

A codeword vector c, having a size of 1×n, can be found by multiplyingthe input data vector v, of the size of 1×k, with a Generator matrix G,which is k×n, as follows:c=v*GThe codeword, the input data and the Generator matrix's symbols, allbelong to a finite Galois Field, preferably they are over the binaryfield. According to this invention all the symbols are over the binaryfield GF(2), it is possible though to group several bits and torepresent smaller vectors and matrices under other finite Galois Fieldsas well.

The block Parity Check Matrix, H, is known as the matrix which isorthogonal to the codeword created by G, hence for every valid codeword:c*H′=0, where H′ is the transposed matrix of H:H′(a,b)=H(b,a). The size of H is (n−k)×n.In LDPC, it is possible to derive the codeword c directly from H,without calculating G. It is possible to perform various manipulationsin the H matrix, in order to adapt it to the characteristics of requiredencoding parameters.

Creating H is not trivial and there may be several solutions for theinternal initial values of the (n−k)×n components in the H matrix.

LDPC can achieve similar or better performance than those of turbocodes, with lower decoder complexity.

Soft input soft output decoder and iterative decoding of the receiveddata block approaches can be used in LDPC, and it can be implementedwithout using interleaver.

DISCLOSURE OF INVENTION

This invention describes a construction of a structured Multi-RateLow-Density Parity-Check (MR-LDPC) code for OFDMA PHY. A basic mothercode is used for deriving various code rates by merging parity checks ofthe mother code. The mother code is constructed using a blockparity-check matrix with cyclic permutation blocks.

All codes derived from the mother code can be implemented on the samehardware of the mother code without additional cost.

Since the basic code is structured, the implementation complexity islow. The codes' parity check matrices have a lower triangularparity-bits section, enabling efficient linear encoding. The newinvention includes flexible matrix's support rates, from ½ to ¾, forboth large and small block size.

This design of the matrices improves the performance of both small andlong blocks relative to rigid matrices, such as those proposed byMotorola and Intel, while using less hardware resources.

According to current invention, it is possible to achieve lineardecoding time with block length for better utilization of hardwareresources. The matrices are designed to converge in a small number ofiteration to reduce latency and hardware complexity. These propertiesare important for minimization of power consumption.

Matrices structure is designed to accommodate the 802.16 OFDMAsub-channel structures of 48 carriers and multiples.

According to current invention, code rate can be changed in a relativelysimple approach while using LDPC.

The matrices which represent block size and/or code rate are easy todesign, and can be optimized to specific requirements.

The novel solution comprises several improvements, thus a new errorcorrecting system and method can be implemented, preferably with theOFDMA 802.16 standard.

The new system and method is expected to be less complex and may consumeless hardware resources than those needed while using turbo codesalternative.

The new approach may present better performance than turbo code, such aswhen it is used with large data block sizes or high data rate. This newinvention gives efficient implementation, which can support many blocksizes and code rates.

According to this invention it is possible to create an H matrix of anydimensions, thus it is possible to set the required n, k easily.

The novel design of the components in this invention offers thesebenefits:

-   1. Adjacent rows are similar—this is helpful in the implementation    of the encoder and decoder for the code.-   2. It is possible to increase the code rate R by uniting a number of    rows. The rows to be united are selected using a novel method, so    that code performance remains good. The row combining method is    proposed to support multi rate with minimal additional complexity.    The scheduling of rows is designed to support the implementation    pipeline to enable fast convergence.-   3. H is designed in such a way as to offer good performance with a    unique design, this refers to the content and allocation of the z×z    matrices in H.-   4. The internal matrices are designed in a novel manner which offers    many benefits.-   5. The novel sizes and dimensions chosen for the internal matrices    and H, offer various benefits, such as the ability to use all of the    available resources in standard 802.16.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 illustrates general block diagram of OFDM data transmissionsystem.

FIG. 2 illustrates general block diagram of OFDM data reception system.

FIG. 3 illustrates general block diagram of data encoding in OFDM.

FIG. 4 illustrates general block diagram of data decoding in OFDM.

FIG. 5 illustrates several cyclic permutation matrices P

FIG. 6 illustrates an arbitrary cyclic permutation matrix P(i)

FIG. 7 illustrates construction of block matrix Hb using permutationmatrices P

FIG. 8 illustrates a method for creating a parity check matrix

FIG. 9 illustrates a flow chart for creating parity check matrices ofmother code Hm

MODES FOR CARRYING OUT THE INVENTION

FIG. 1 illustrates general block diagram of OFDM data transmissionsystem.

FIG. 2 illustrates general block diagram of OFDM data reception system.

The benefits described in this invention may be implemented in oneembodiment at the encoder 200 and/or decoder 400. According to oneembodiment there is no need to use interleaver or deinterleaver means110, 370 respectively in such a system.

FIG. 3 illustrates general block diagram of data encoding in OFDM.

FIG. 4 illustrates general block diagram of data decoding in OFDM.

This invention may be implemented in any of these blocks, and especiallyin inner encoder/decoder means 230, 420 respectively. Interleaver anddeinterleaver means are optional with respect to this invention.

This invention may be implemented in outer encoder/decoder means 210,440 respectively. Outer encoding means are optional as well with respectto this invention.

The systems and methods described hereinafter may be used according inOFDMA systems, and especially with such systems which are designedaccording to the 802.16 standard. According to the new invention, the Hmatrix can be divided into two matrices:H=[H1|H2]The codeword can be divided into two vectors:c=[v|Parity]where v is the input data vector (1×k), and Parity is the parity checkvector, which is in the size of 1×(n−k).

From the previous definition that c*H′=0, an equivalent formula is:H*c′=0which can be written as:[H1|H2]*[v|parity]′=0.

From the last equation we derive:H1*v=H2*parityand:parity=(inv(H2)*H1)*vinv(H2) is the inverse matrix of H2. The inverse matrix of H2 can beeasily found as H2 is set to be a lower triangular matrix.

The dimensions of H1 are (n−k)×k, and of H2 are: (n−k)×(n−k). Thus, thecodeword c can be easily constructed:c=[v|Parity]

A rate for the code, R is defined as the ratio between the length of theinput data vector and the codeword vector c, thus: R=k/n.

Since k is the length of v, and n is the length of c, the rate R can beset by setting the dimensions of H:

The height of H is: n−k

The width of H is: n

One of the benefits of this invention is using such a matrix H whichallows to unite (collate) two rows or more into one new row, by addingthe rows.

As a result of uniting rows, the height of the H matrix is reduced, thusn remains the same but k is increased since there will be less rows.

By using this method, it is possible to use a shorter input data vector,with more parity check symbols.

Using this approach it is possible to easily change code rate R.

This approach can be implemented using less hardware resources, eventhough the code characteristics may be changed.

H is such that each of its internal components is a squared matrix withthe dimensions z×z. The special parameter z can be changed in order todetermine the size of these internal matrices, which are also referredas: “small z×z blocks”.

According to this paper, a basic block matrix Hb, is used from which aparity check matrix of mother code H or Hm can be created, usingexisting or novel systems and methods.

The internal squared matrices are marked as: 0, P(0) . . . P(z−1), P(st)0 is the zero matrix.

-   P(st) is a stairs matrix.-   P(0) is the identity matrix.-   P(i), 0<i<z, is p(0) after i cyclic movements to the right of the    components in each row. A component which is shifted from the end of    the line, is shifted to the leftmost location in that line.

By changing the z parameter, it is possible to change the size of H1, H2and H altogether. Thus, the size of the codeword: n, the size ofinformation vector: k, and the number of parity check symbols: n−k, canbe easily increased by increasing z.

In one embodiment, the mother code is a length N_(m) rate ½ systematicstructured LDPC code. The parity-check matrix of the mother code H_(m)is constructed using a

$\frac{N_{m}}{2Z} \times \frac{N_{m}}{Z}$block matrix H_(b) or Hb, consisting of small Z×Z blocks, which areeither the zero matrices or a cyclic permutation matrix. For brevity ofnotation we denote the dimensions of the block matrix by

$M_{b} = \frac{N_{m}}{2Z}$ and $N_{b} = {\frac{N_{m}}{Z}.}$

FIG. 5 illustrates several cyclic permutation matrices P, it can be seenthat the Z matrices P(0) to P(Z−1) can be created using cyclic shifts,as indicated by the arrow above P(1). P(st) can be created by addingmatrices P(0) and P(Z−1).

FIG. 6 illustrates an arbitrary cyclic permutation matrix P(i), in orderto create matrices P(0) to P(Z−1), the following method can be used.

The method for building permutation matrices P(i), may include:

-   -   1. Define an integer value Z.    -   2. Create an initial matrix, preferably P⁰, which is the        identity matrix.    -   3. By using one cyclic shift right, to each row, it is possible        to create P(1), the one and zeros in rightmost locations are        shifted to the leftmost cell in that line.    -   4. This operation is repeated Z−2 times, creating P(0) . . . to        P(Z−1).    -   5. An additional stairs matrix P(st), is created as well.

According to this method, Z permutation matrices in the size of Z×Z arecreated, for the purpose of later using them to construct H, Hb, Hm orany other LDPC and/or Parity check related matrix.

Z is an integer parameter, which can be initially defined according tomatrix size, hardware and performance considerations.

In two preferred embodiments Z is either 12 or 24, which is useful forOFDMA, however other values can be defined as well.

P(st) the stairs matrix can be created in any stage, or in other methodssuch as by summing existing matrices: P(st)=P(0)+P(Z−1)

The initial matrix may be P(0) or any other matrix. Cyclic shifts may beperformed to the left, Creating P(Z−1), P(Z−2) . . . or to the right.

It is possible to store P matrices in any type of digital memory orstorage means, and to read them from that source. According to thismethod it is easy to create P matrices of any Z×Z size easily.

FIG. 7 illustrates construction of block matrix Hb using permutationmatrices P

This matrix is created using Z×Z matrices including the zero matrix 0.The overall size of this matrix is (N_(m)/2)×N_(m) since the height is:n−k=N_(m)/2 and the width is n=N_(m) then the initial code rate isR=(n−k)/n=0.5

This matrix, also referred as “block matrix”, Hb or Hb includes

$\frac{N_{m}}{2Z} \times \frac{N_{m}}{Z}$matrices, consisting of small Z×Z blocks, which may include one or moreof: the zero matrix, P(st) and P(i).

The dimensions of the block matrix is

$M_{b} = \frac{N_{m}}{2Z}$rows of and

$N_{b} = {\frac{N_{m}}{Z}.}$columns of Z×Z matrices.

As shown in the figure, the N_(b) block columns of the blockparity-check matrix are divided to sets S₁, S₂ . . . , S₇ by numberingthem as follows: 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 . . .According to the embodiment shown in this figure, N_(b)=16 and thematrices columns are numbered: 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2.

FIG. 8 illustrates a method for creating a parity check matrix, themethod for creating a parity check matrix comprises:

A. Creating the Hb matrix 820, which should satisfy the followingrequirements:

-   -   1. The M_(b)×M_(b) right side of the matrix is lower triangular.    -   2. The lower rightmost block of the matrix is P^(st).    -   3. Each row in the block matrix contains 6 or 7 non-zero block        entries belonging to different sets of columns, i.e. a row        cannot contain more than one block entry from any set S_(j),        jε{1, . . . , 7}.    -   4. H_(b) is an irregular matrix, such that the block columns        weights spectrum is optimized for providing good code        performance in a small number of decoding iterations. (a block        column's weight is the number of non-zero block entries in a        column).    -   5. Rows j and

$j + \frac{M_{b}}{2}$for

${j = 1},\ldots\mspace{14mu},\frac{M_{b}}{2}$have no overlapping non-zero block entries.

-   -   6. H_(m/2) denote the resulting parity-check matrix that is        obtained by summing up the lower and upper

$\frac{M_{b}}{2} \times N_{b}$parts the block matrix H_(b). Then, the resulting parity check matricesH_(m) and H_(m/2) do not contain short cycles.

FIG. 7 illustrates one embodiment of constructing the block matrix Hbusing permutation matrices P. According to one embodiment, withreference to this figure, N_(m)=384, Z=24 and there are 8×16 permutationmatrices in Hb.

B. Deriving codes of various rates from the mother code 830

Codes of various rates between ½ and ¾ can be derived from the mothercode by summing up pairs of rows of the block matrix H_(b), in this waycreating the H or Hm matrix.

A code of rate

$\frac{1}{2} + \frac{\alpha}{N_{b}}$for any

$\alpha \in \left\{ {0,\ldots\mspace{14mu},\frac{N_{b}}{4}} \right\}$can be obtained by summing up the rows j and

$j + \frac{M_{b}}{2}$for j=1, . . . , α. The resulting block matrix after summation is a(M_(b)−α)×N_(b), hence the code rate is

${1 - \frac{M_{b} - \alpha}{N_{b}}} = {\frac{1}{2} + {\frac{\alpha}{N_{b}}.}}$

Because of requirement A.5 of the constructed mother code, the resultingmatrix after summation remains a block matrix with permutation blocks asits entries. All derived codes are of length N_(m). All derived codeshave the same number of 1's in their parity-check matrix because ofrequirement A.5.

According to another embodiment, when using one or more of theabovementioned methods, encoding can be made more efficiently.

All the constructed codes have a lower triangular block parity-checkmatrix; hence they have a very simple linear encoding based on Gaussianelimination.

Encoding can be performed using the decoder by initializing theinformation bits part of the decoder input messages with the informationbits and the parity bits part of the decoder input messages witherasures. Then the decoder can (always) recover the erased bits due tothe lower triangular structure of the parity check matrix. If the paritychecks are processed one after another by the decoder, then in eachcheck only a single bit is unknown and the decoder sets this bit to bethe XOR of the 6 (or 5) known bits in the check.

According to another embodiment, when using one or more of theabovementioned methods, decoding can be made more efficiently;

Since the block rows of the parity check matrices can be arranged insuch a way that no two consecutive block rows have overlapping non-zeroblock entries, for example in the new matrix the rows can be sorted inthe order 1, 13, 2, 14, 3, 15, . . . , 12, 24 to satisfy this property.The incentive is that when using a layered BP decoder, for example, inwhich block rows are updated serially one after another—when updating ablock row, messages corresponding to the non-zero locations in the blockrow are read from memory into processing units, updated and written backto memory. This process requires several clocks to complete, thus a pipemay be used.

In this way each clock it is possible to process another block row.However once a message is read from the memory, till it is written back(while the message is in the processor pipe), it cannot be used again.Thus it should not appear in the consecutive block row that isprocessed, otherwise the pipe should be stalled and this would causehardware inefficiency and reduce the maximal number of iterations thatcan be supported.

Thus, this invention offers a more efficient decoding solution, since itmay better support pipeline implementation.

FIG. 9 illustrates a flow chart for creating parity check matrices ofmother code Hm,

The method herein may be used after loading or setting Hb 910, or Hb maybe set in any manner as already described, such as according the method930 described in regards to FIG. 8, which described how to create Hm orH 930 out of Hb.

According to current method, various code lengths can be accommodatedusing any of the following methods, as required or defined for selectingthe preferred method 940, can be performed:

-   -   1. Shortening the mother code and its derivatives 960: shorter        codes can be obtained by shortening each of the length N_(m)        codes of rates ½ to ¾ that are obtained from the mother code.        Any pair of code length N_(m) and code rate R_(c) maintaining

$\frac{N_{m}}{4} \leq {N_{c}\left( {1 - R_{c}} \right)} \leq \frac{N_{m}}{2}$can be obtained by shortening one of the length N_(m) codes. Hence,larger flexibility in code length and rate is obtained compared to usinga single rate mother code.

-   -   2. Changing the size Z of the permutation blocks 970, which        inflates/deflates the parity-check matrix.

Both of the methods described above can be used, however they sufferfrom the same disadvantage: the decoding time remains the sameregardless of the code length. When shortening is used the decoder stillworks on the complete code even though the actual code length might bevery small and the decoding time of short and long blocks is the same.When the permutation block size Z is used for changing the code length,the effect is the same. The block matrix structure allows to process Zrows or columns of the parity check matrix simultaneously using Zprocessors. When we “deflate” the permutation block size by factor α weobtain a shorter code of length αN_(m), but it also means that only αZprocessors are active. Hence, the hardware is not used efficiently, andthe decoding time of the length αN_(m) code remains the same as thedecoding time of a length N_(m) code.

According a preferred embodiment in this invention, novel matrices'dimensions are chosen, to better support OFDMA systems, which use LDPC.According to this embodiment, there are 48 carriers in each OFDMAsub-channel, modulation may include QPSK, 16 QAM or 64 QAM, each require2, 4 or 6 bits, respectively. QPSK supports 48×2=96 bits, 16 QAM48×4=192 bits, and 64QAM 48×6=288 bits.

It may be possible to select the preferred modulation method, and so inorder to use available hardware resources efficiently the followingunique value for n may be used:

-   576=(48×2)×6, for QPSK.-   576=(48×4)×3, for 16 QAM.-   576=(48×6)×2, for 64 QAM.

Thus according to this embodiment every value which is related to n,which is the length of the codeword, may have the length of 576 or itsmultiple. Preferred values for the width of Hb would include: 576, 1152,1728, 2304, and so on.

In a novel embodiment, it is possible to use several mother codes 950,with different lengths. According to a preferred embodiment it ispossible to use four mother codes of lengths N_(m)=2304, 1728, 1152, 576with Z=12, Z=24 or other Z values. The code lengths are chosen asmultiples of 48 bits to accommodate an integer number of OFDMAsub-channels. According to one embodiment, the permutation block sizecan be Z=12 for providing the possibility for sufficient parallelism toallow enough decoding iterations at high throughput and sever latencyconditions as described.

All of the mother codes and the codes derived from them can beimplemented on the same hardware. Adding each additional mother code mayrequire only a ROM for maintaining its block parity check matrix Hb.

In one embodiment, the ROM size required for maintaining the matrixH_(b) is

$\frac{7N_{m}}{2Z} \times \left( {\left\lceil {\log_{2}\frac{N_{m}}{Z}} \right\rceil + \left\lceil {\log_{2}Z} \right\rceil} \right)$bits. For the largest length 2304 code this amounts to 4032 bit ROM. Formaintaining all 4 mother codes a 9744 bit ROM is needed. Thus, at a lowcost of an increased ROM size we obtain full rate and code lengthflexibility.

The same encoder/decoder hardware supports lengths 2304, 1728, 1152 and576 codes of any rate between ½ and ¾. Obtaining other code lengthbetween the 4 mother codes' lengths is done through the shorteningmechanism.

The advantage of this method is that the decoding time is linear withthe code length since all mother codes are constructed using 12×12permutation blocks. This provides a good solution for both streamingapplications and immediate ACK applications. In streaming applications,codes of different length perform the same number of iterations for agiven throughput (while in the first two methods the performance ofshorter codes would be severely impaired because they will be able toperform less decoding iterations). In immediate ACK applications shortercodes can be used when lower latency is needed.

It is possible to use Structured and/or Random code construction.Relevant code parameters and system parameters include:

-   N—code length-   R—code rate-   M=N(1−R)—number of rows in the parity-check matrix-   d_(c) —average parity-check matrix row weight-   I—desired maximal number of iterations (assuming no statistical    multiplexing is used)-   f—system clock-   Z—decoder parallelism (number of processors)-   L—decoding latency

The standard decoding algorithms for LDPC codes are based on iterativemessage-passing algorithms. These algorithms rely on a graph-basedrepresentation of codes, where the decoding can be understood as messagepassing between nodes in a bipartite graph. In each iteration, messagesare passed on all edges of the graph in both directions. The number ofedges in the graph is equal to the number of 1's in the code'sparity-check matrix, which is M×d_(c). Hence, a decoding iterationinvolves reading M×d_(c) messages from a memory, processing the messagesand writing the updated messages back to memory. Assuming requireddecoding latency L, a system clock frequency f and a desired maximalnumber of iterations I, a decoding iteration should be performed in

$\frac{fL}{I}$clocks. This means that in each clock

$\frac{{Md}_{c}I}{fL}$messages should be read (and written) to the memory. One can thenimmediately see that many messages should be read each clock from thememory. This implies that using a randomly constructed LDPC code wouldrequire saving the messages in registers (since

$\frac{{Md}_{c}I}{fL}\text{-}{port}\mspace{14mu}{RAM}$do not exist) leading to increased chip area. Furthermore, it would leadto severe routing problems of messages into processors, rendering thedesign impractical.

Using a structured block LDPC code can solve these problems, enablingsimple simultaneous processing of sets of Z messages, by facilitatingboth their memory management and their routing from the memory to theprocessing units.

It is possible to repeat the process 980, thus using any combination ofmethods 920, 930, 950, 960 and 970 and to end it when required 990.

Simulation results for several methods, which include comparisons toother codes and explanations are detailed in: Provisional 1: “6.Simulation results” and Provisional 2: “7. Simulation results”.

Industrial Applicability

The present invention refers to improvements in wireless communications.It describes a construction of a structured Multi-Rate Low-DensityParity-Check (MR-LDPC) code for OFDMA PHY. A basic mother code is usedfor deriving various code rates by merging parity checks of the mothercode. The mother code is constructed using a block parity-check matrixwith cyclic permutation blocks.

All codes derived from the mother code can be implemented on the samehardware of the mother code without additional cost.

Since the basic code is structured, the implementation complexity islow. The codes' parity check matrices have a lower triangularparity-bits section, enabling efficient linear encoding. The newinvention includes flexible matrix's support rates, from ½ to ¾, forboth large and small block size.

1. A communications system which uses LDPC and comprises permutationmatrices P of size Z×Z comprising a plurality of matrices P(0) . . .P(Z−1) and a stairs matrix P(st), from which a block parity check matrixH_(b) is constructed, using only the permutation matrices P:P(0) . . .P(Z−1), the stairs matrix P(st) and a zero matrix 0, wherein the initialdimensions of H_(b) are: 0.5 Nm×Nm or 0.5 n×n, wherein n is an integerrepresenting a codeword vector length, wherein the height of the blockparity check matrix H_(b) is half of its width and wherein the initialcode rate represented by the block parity check matrix H_(b) is:R=(n−k)/n=0.5, wherein the initial H_(b) is as shown with regards toFIG.
 7. 2. A communications system which uses LDPC and comprisespermutation matrices P of size Z×Z comprising a plurality of matricesP(0) . . . P(Z−1) and a stairs matrix P(st), from which a block paritycheck matrix H_(b) is constructed, using only the permutation matricesP: P(0) . . . P(Z−1), the stairs matrix P(st) and a zero matrix 0,wherein the initial dimensions of H_(b) are: 0.5 Nm×Nm or 0.5 n×n,wherein n is an integer representing a codeword vector length, whereinthe height of the block parity check matrix H_(b) is half of its widthand wherein the initial code rate represented by the block parity checkmatrix H_(b) is: R=(n−k)/n=0.5, wherein the initial dimensions of theblock parity check matrix H_(b) are referenced by the Z×Z matrices, anddenoted by M_(b) ×N_(b), and is such to satisfy the following: a. TheM_(b) ×M_(b) right side of the matrix is lower triangular; b. The lowerrightmost block of the matrix is P(st)=P^(st); c. Each row in the blockmatrix contains 6 or 7 non-zero block entries belonging to differentsets of columns; d. H_(b) is an irregular matrix, such that the blockcolumns weights spectrum is optimized for providing good codeperformance in a small number of decoding iterations (ablock column'sweidght is the number of non-zero block entries in a column); e. Rows jand j+Mb/2 for j=1 . . . Mb/2 have non-overlapping non-zero blockentries; wherein a method for deriving a plurality of codes of variousrates from a mother code is implemented by summing up pairs of rows ofthe block matrix H_(b) creating an H or Hm matrix, as follows:
 1. Decidethe required code rate: $R = {\frac{1}{2} + \frac{\alpha}{N_{b}}}$  forany${\alpha \in \left\{ {0,\ldots\mspace{20mu},\frac{N_{b}}{4}} \right\}};$2. Repeat summing up the rows j and $j + \frac{M_{b}}{2}$  for _(j) =1,.. . , α;
 3. The resulting block matrix after summation is a(M_(b)α)×N_(b), hence the code rate is${{1 - \frac{M_{b} - \alpha}{N_{b}}} = {\frac{1}{2} + \frac{\alpha}{N_{b}}}};$wherein the constructed mother code or the resulting matrix aftersummation remains a block matrix with permutation blocks as its entriesand wherein said plurality of derived codes are of length N_(m) with thesame number of 1′s in their parity-check matrix.
 3. The communicationssystem of claim 2, wherein encoding is done using the decoder byinitializing the information bits part of the decoder input messageswith the information bits and the parity bits part of the decoder inputmessages with erasures; the decoder is capable of recovering the erasedbits due to the lower triangular structure of the parity check matrix.4. The communications system of claim 3, wherein parity checks areprocessed one after another by the decoder, thus in each check only asingle bit is unknown and the decoder sets this bit to be the XOR of the6 (or 5) known bits in the check.
 5. The communications system of claim2, wherein decoding is done more efficiently, since the block rows ofthe parity check matrices are arranged in such a way that no twoconsecutive block rows have overlapping non-zero block entries(requirement e in claim 2 then when using a layered BP or equivalentdecoder, in which block rows are updated serially one after another; andsince when updating a block row messages corresponding to the non-zerolocations in the block row are read from memory into processing unitsmeans updated and written back to memory; and since this processrequires several clocks to complete, and is preferably implemented usingpipe means; then it is possible in each clock to process another blockrow; thus a message is read from the memory and is written back (whilethe message is in the processor pipe), even though it cannot be usedagain; thus since it does not appear in the consecutive block row thatis processed, the pipe is not stalled and the hardware is moreefficient, reducing the maximal number of iterations.
 6. Acommunications system which uses LDPC and comprises permutation matricesP of size Z×Z comprising a plurality of matrices P(0) . . . P(Z−1) and astairs matrix P(st), from which a block parity check matrix H_(b) isconstructed, using only the permutation matrices P: P(0) . . . P(Z−1),the stairs matrix P(st) and a zero matrix 0, wherein the initialdimensions of H_(b) are: 0.5 Nm×Nm or 0.5 n×n, wherein n is an integerrepresenting a codeword vector length, wherein the height of the blockparity check matrix H_(b) is half of its width and wherein the initialcode rate represented by the block parity check matrix H_(b) is:R=(n−k)/n=0.5, wherein the initial dimensions of the block parity checkmatrix H_(b) are referenced by the Z×Z matrices, and denoted by M_(b)×N_(b), and is such to satisfy the following: a. The M_(b) ×M_(b) rightside of the matrix is lower triangular; b. The lower rightmost block ofthe matrix is P(st)=P^(st); c. Each row in the block matrix contains 6or 7 non-zero block entries belonging to different sets of columns; d.H_(b) is an irregular matrix, such that the block columns weightsspectrum is optimized for providing good code performance in a smallnumber of decoding iterations (ablock column's weidght is the number ofnon-zero block entries in a column); e. Rows j and j+Mb/2 for j=1 . . .Mb/2 have non-overlapping non-zero block entries; wherein four mothercodes of lengths N_(m)=2304, 1728, 1152, 576 are used, with Z=12, Z=24or other Z multiples of 48 bits to accommodate an integer number ofOFDMA sub-channels.
 7. The communications system of claim 6, whereinZ=12, allowing using the same hardware for different codes; adding eachadditional mother code requires only a ROM or equivalent means formaintaining its block parity check matrix H_(b).
 8. The communicationssystem of claim 7, wherein the size of memory means required formaintaining the matrix H_(b) is$\frac{7N_{m}}{2Z} \times \left( {\left\lceil {\log_{2}\frac{N_{m}}{Z}} \right\rceil + \left\lceil {\log_{2}Z} \right\rceil} \right)$bits; for code length 2304 this amounts to 4032 bits; for maintainingall four mother codes a 9744 bits memory is needed, thus at a low cost afull rate code length flexibility is obtained.
 9. The communicationssystem of claim 8, wherein one or more ROMs are used as memory means.